The present invention relates in general to digital clock generating systems and more particularly to the phase detector component of a digital phase locked loop (DPLL).
In modern digital telecommunication switching systems voice samples are transferred from central office to central office and within a central office as digital information. To preserve the integrity of this digital information and thus insure high quality voice communication, the telecommunication network is synchronized.
Therefore, it is a requirement for a central office telephone switching system to synchronize its local clock (slave) to that of the network (reference). Synchronization of the slave clock must be very precise and accurate as other offices may be synchronized to this central office's clock.
Synchronization between two clocks is best done by the use of a Phase Locked Loop (PLL). The concept of the PLL is well known and old in the art, but until recently the PLL function has been implemented predominantly by analog methods. With an analog phase locked loop the loop characteristics are fixed by analog components and cannot easily be changed.
A central office telephone switching system requires the PLL to have dynamic loop characteristics. Since a digital phase locked loop (DPLL) can have programmable loop characteristics, it has become the predominant PLL for such systems.
One critical element of a DPLL is the phase detector circuit which provides a numerical value proportional to the phase difference between the reference and slave signals. The phase detector circuits in prior art systems require either frequency count-down circuits or very high frequency clocks.
Frequency count-down circuits divide the fundamental frequency by an integer value and produce a phase difference value with an inherent error of plus or minus one. This error produces an uncertainty in the exact phase relationship of the slave to the reference. For most applications this type of phase detector works fine and does not cause any problems. However, central office telephone switching systems require that the clock which supplies timing pulses to the switching network, be phase locked to within a few degrees of a known reference.
Phase detectors employing very high frequency clocks may be employed to measure small phase differences at the fundamental frequency, but resolution of the phase detector is directly dependent on the clock frequency. A 100 MHz clock can resolve a 10 ns phase error, a 1 GHz clock can resolve a 1 ns error, . . . etc. Gating and counting circuits using such a fast clock are impractical and expensive for a central office telephone systems.
Accordingly, it is an objective of the present invention to provide a highly accurate phase detector circuit for determining the phase relationship of two signals in a DPLL.